CSS 2025 Computer Science Combined Papers Past Paper

Paper details

Examination

CSS

Year

2025

Subject

Computer Science

Paper

Combined Papers

Subject type

Optional

Mode

Subjective

Questions recorded from this paper

These 12 question wordings are transcribed from CSS Vista’s structured Computer Science past-paper record for CSS 2025.

1. Q2 · Introduction to Computing(a) How is the Generative AI creating impacts on our society? Discuss the benefits and (6) challenges associated with its use. Support your answer by adding examples. (b) Provide a comparison of different data storage devices in terms of speed, size, access time (6) and cost. (c) What are Two's Complement numbers? Explain the working of it with examples. Discuss (8) the practical scenarios where these numbers are used.
2. Q4 · Program structure(a) Write a C++ program to output the arithmetic series of n terms. The series formula for (6) n calculating the sum of n terms is as follows: Sn = [2a + (n-1) d] , with values a = 5, d= 3 and n= 6, where a = first term, d= common difference and n = number of terms. (b) Write a C++ program to calculate and display the product of two matrices of order 2 x 2. (6) The program should prompt the user to provide values of both matrices (c) Write a C++ program to demonstrate the two different complex numbers using structure. (8) The program should use function to calculate the sum of complex numbers and display their result in the specific format such as (a + bi), where a and b are the real and imaginary part respectively and i is imaginary unit such as i = √−1.
3. Q3 · objects(a) What is the difference between shallow copy and deep copy of creating objects in C++. (6) Discuss the cases where a specific copy should be used by providing examples. (b) State the difference between const keyword and static keyword in C++. Illustrate each (6) keyword with suitable examples. (c) Explain the role of pure virtual functions in implementing abstract classes in C++. How do (8) they differ from virtual functions? Give an example of C++ classes where both types of functions are used.
4. Q5 · data members(a) Demonstrate the use of stream insertion and extraction operators for creating custom (10) objects. Provide a suitable coding example for illustrating the functional difference between them. (b) Implement a Book Management System consisting of three different classes. The book (10) class should have data members such as book name, ISBN number, and publication year. The author class should have attributes such as author name, and author email. The publisher class contains attributes such as publisher name, publisher email and publisher address. Each book has an author and a publisher. The author and publisher are created and destroyed with books. When the book is deleted, the corresponding author and publisher should also be deleted. Write a C++ code of this system and explain how the composition relationship is used in this system.
5. Q6 · Binary Search trees(a) What are self-balancing Binary Search Trees? Under what circumstances, the self- (6) balancing Binary Search Trees are preferred over Binary Search Tree? (b) Give pseudocode of implementing Fibonacci sequence recursively. Find the time (6) complexity of this approach and explain how it is calculated. (c) Suppose you are the owner of a small manufacturing company that delivers goods to (8) customers. During the sale season, you received a huge number of orders. To efficiently manage the orders, you need to sort the packages based on their weights. You are provided with the weights of 10 parcels (in kilograms) as shown below. Use the quick sort method to sort these parcels in ascending order. Weights: [30, 45, 10, 20, 75, 15, 85, 40, 05, 65] Clearly indicate the choice of pivot and reason for it. Provide a graphical representation with explanation at each step.
6. Q7 · Process Improvement(a) A project management involves different types of planning stages to finalize the project. (6) Discuss the different types of planning phases conducted during software development with list of specific tasks performed during each planning stage. (b) Illustrate the difference between software validation and software verification testing (6) techniques. Give examples to strengthen your answer. Clearly elaborate the case where each type of technique should be used. (c) What is the Software Process Improvement (SPI) framework? Highlight the different steps (8) of SPI framework and the key elements involved. Also provide the description of the models used within SPI framework and how to determine the projects for which SPI framework should be used.
7. Q8 · Finite automata(a) Create a regular expression for the language that always starts with string “ baa ”. Also (6) draw the deterministic finite automata (DFA) for such language. Provide a clear explanation of each step. (b) What is Instruction Scheduling? Explain its role during code generation process. (6) (c) What is a parse tree? How the parse tree is used to check whether a specific string belongs (8) to a language or not. Provide example to elaborate this.
8. Q4 · Instruction execution cycle(a) A benchmark program is run on a 40 MHz processor. The executed program consists (10) of 100,000 instruction executions, with the following instruction mix and clock cycle count: Instruction Type Instruction Count Cycles per Instruction Integer arithmetic 45,000 1 Data transfer 32,000 2 Floating point 15,000 2 Control transfer 8000 2 Determine the effective CPI, MIPS rate, and execution time for this program. (b) What are the differences among sequential access, direct access, and random access? (10) Also, write and explain the general relationship among access time, memory cost, and capacity.
9. Q2 · Parallel Processing(a) An instruction requires five stages to execute: (3) Stage-1 (instruction fetch) requires = 30 ns Stage-2 (instruction decode) = 9 ns Stage-3 (instruction execute) = 20 ns Stage-4 (Memory access) = 35 ns Stage-5 (Store results) = 10 ns An instruction must proceed through the stages in sequence. What is the minimum asynchronous time for any single instruction to complete? (b) Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a firstword (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. (i) What is the access time when there is a cache miss? Assume that the cache (3) waits until the line has been fetched from main memory and then re-executes for a hit. (ii) Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does (4) this reduce the average memory access time? (c) (i) Compare the set of addressing modes of RISC and CISC machines. Give one (5) example of addressing modes used in RISC and CISC respectively. (ii) Explain Parallel Processing, and also draw pipeline processing for instruction: (5) Ai*Bi+Ci
10. Q3 · HTTP(a) Answer the Following Questions: (i) Is it possible for an organization’s Web server and mail server to have exactly (2) the same alias for a hostname (for example, foo.com)? What would be the type for the RR that contains the hostname of the mail server? (ii) Draw the structure of Internet in terms of ISPs, also show the concept in terms (3) of Edge and Core networks. (iii) A packet switch receives a packet to be forwarded. When the packet arrives, (3) one other packet is halfway done being transmitted on this outbound link and four other packets are waiting to be transmitted in FIFO manner. Suppose all packets are 1,500 bytes and the link rate is 2 Mbps. What is the queuing delay for the packet? (iv) Why do HTTP, FTP, SMTP, and POP3 run on top of TCP rather than on UDP? (2) (b) (i) Why do we need conditional GET when we have regular GET with respect to (4) HTTP? What is its difference in comparison to GET? (ii) With respect to web caching, if an average object size is 100K bits and the (6) average request rate from browsers to origin servers is 15/sec. Suppose RTT from an institutional router to any origin server is 2 sec. If LAN speed is 100Mbps and access link speed is 1.54 Mbps then with a cache hit of 50%, how much total delay will be there?
11. Q5 · Virtual Memory Management(a) Consider the following pseudo code for producer and consumer: // producerdo{ // consumerdo{ //produce an item // remove item from buffer //place in buffer // consumes item }while(true); }while(true); (i) What is race condition? (ii) Is there any possibility of the race condition if two threads named producer and consumer simultaneously execute the above functions? Provide the reasoning in two-three sentences. (iii) Add the necessary synchronization in the above functions, you may use (3) semaphores or mutex. You may provide just pseudo code or exact C/C++ code. (iv) Consider a process that uses a user level threading library to spawn 10 user level (3) threads. The library maps these 10 threads on to 2 kernel threads. The process is executing on a 8-core system. What is the maximum number of threads of a process that can be executing in parallel? (b) Consider a multi-level memory management scheme with the following format for virtual addresses: Virtual Page # Virtual Page # Offset (10 bits) (10 bits) (12 bits) Virtual addresses are translated into physical addresses of the following form: Physical Page # Offset (20 bits) (12 bits) Page table entries (PTE) are 32 bits and contain the 20-bit physical page number and OS bookkeeping bits (e.g., valid, dirty, used, etc.). (i) How big is a page? (1) (ii) What is the maximum amount of memory (in bytes) in a single virtual address (3) space? Explain your answer. (iii) What is the maximum amount of physical memory (in bytes) that this memory (3) management scheme supports? Explain your answer. (iv) Sketch the format of the page table for the multi-level virtual memory (3) management scheme. Illustrate the process of resolving an address as well as possible. Assume there is no TLB or cache.
12. Q7 · Scaling(a) In the context of compression, differentiate between coding, spatial and temporal (6) redundancies. (b) What is translation and scaling? Find the number of bits required to store a 256x256 (6) image with 32 gray levels. (c) What is Histogram equalization? Explain the process and discuss its uses. (8)

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