Paper II covers how complete computer systems actually work: architecture describes the machine itself, operating systems manage its resources, networks connect machines together, databases preserve structured data, image processing manipulates digital images, and web technologies build networked applications on top of all of this. For architecture specifically, the reliable approach is to draw the data path and trace how instructions or operands actually move through registers, memory, buses, and processing units — then connect each design choice to its effect on performance, cost, complexity, or parallelism. Terms like cache, pipeline, RISC, or bus should never be treated as isolated hardware vocabulary; each one solves a specific, identifiable performance or organization problem.
A. Architecture Fundamentals and Performance
Computer architecture describes the programmer-visible structure and design choices of a system; computer organization describes how the actual physical components implement that architecture underneath. Architectural levels can hide lower-level detail from higher levels through abstraction, sometimes formalized as virtual machines. Performance depends on the actual workload, instruction count, cycles required per instruction, clock rate, memory behaviour, and I/O — never on clock speed in isolation. Example: a processor with a higher clock rate can still finish a task more slowly overall if it requires substantially more cycles per instruction, or spends more time waiting on memory access, than a lower-clocked but more efficient alternative. The instruction cycle broadly proceeds through fetch (retrieve the next instruction), decode (interpret what it means), and execute (carry it out) — this three-stage rhythm is the basic heartbeat underlying every instruction a processor runs.
B. CISC vs RISC, Parallelism, and Data Representation
CISC (complex instruction set computing) traditionally uses richer, more complex individual instructions; RISC (reduced instruction set computing) emphasizes simpler operations that can be pipelined more efficiently — though modern real-world processors often blend ideas from both philosophies rather than representing either approach in pure textbook form. Parallelism means performing multiple operations at once, or overlapping their execution in time rather than running them strictly one after another. Example: pipelining overlaps different stages of several instructions simultaneously, much like an assembly line handles different physical products at different stages of production at the same time, rather than finishing one product completely before starting the next. Data representation covers both internal representation (integers, floating-point numbers, and character encodings as the processor actually manipulates them) and external representation (the formats used specifically for communication or storage interfaces, which may differ from internal representation).
C. Memory Hierarchy and I/O
Processors, memory, and I/O devices exchange information through interconnections such as buses and point-to-point links, which carry data, addresses, and control signals in the classic model. Memory hierarchy balances speed, cost, and capacity against each other: registers are tiny and fastest, caches reduce average access time for frequently used data, main memory is much larger but slower than either, and secondary storage is larger still but far slower than main memory. This entire hierarchy works specifically because of locality of reference — the tendency of real programs to repeatedly access the same, or nearby, data and instructions over short periods of time. Example: a program that repeatedly works with the same small data set runs faster precisely because that data stays resident in fast cache rather than needing to be fetched from slower main memory on every single access.
I/O systems connect the CPU and memory with external devices, and can be organized as programmed I/O (the CPU actively manages every transfer step), interrupt-driven I/O (the device signals the CPU only when it needs attention), or direct memory access, DMA (a dedicated controller transfers entire blocks of data between a device and memory with far less direct CPU involvement than moving every single word through CPU instructions). Computer arithmetic implements mathematical operations within finite binary representations, which inherently creates overflow and precision issues that do not arise in ordinary unbounded mathematics — a microprocessor integrates a full set of CPU functions onto a single integrated circuit, and understanding these finite-arithmetic limitations matters for correctly reasoning about numerical edge cases in real programs.
D. Processor Structure, Control, and Parallel Processing
The processor contains datapath components (which actually carry out computation) and control logic (which directs which operations happen, and when). The control unit specifically issues the signals needed to correctly execute each instruction, and this can be implemented either as hardwired control (control signals produced directly by fixed digital logic) or microprogrammed control (control signals produced by executing microinstructions stored in a dedicated control store) — each approach trades flexibility against raw speed differently. Instruction-level parallelism and superscalar processor designs try to execute multiple independent instruction operations concurrently within a single processor core; example: two genuinely independent arithmetic instructions can sometimes execute in parallel, but a data dependency between them (where one instruction needs the other’s result) can prevent this parallelism from being exploited. Multiprocessor systems (multiple separate processors) and multicore systems (multiple processing cores on a single chip) both provide multiple processing units, but achieving actual speedup from either requires that the workload itself can genuinely be divided into independent, parallelizable pieces — parallel hardware alone cannot speed up inherently sequential work.
Computer Architecture key takeaways: performance depends on the interaction of instruction count, cycles per instruction, clock rate, memory behaviour, and I/O together, never on clock speed alone. CISC and RISC represent different philosophies about instruction complexity, and modern processors often blend both. The memory hierarchy exists, and actually works, specifically because of locality of reference in real program behaviour. DMA reduces CPU involvement in bulk data transfers compared to fully CPU-managed I/O. Hardwired and microprogrammed control trade flexibility against speed differently. Parallel hardware can only speed up work that is genuinely divisible into independent pieces — it cannot accelerate inherently sequential computation.